✖️ Array Multiplier

Capstone: 8-bit multiplier built from AND gates and full adders. See partial products, carry propagation, and the full array structure.

Result

A × B =
0

A

B

Product

Partial Products (AND Array)

Each row = A[i] AND B. Rows are shifted left by i positions. Full adders reduce the array.

Block Diagram — Array Multiplier Architecture

How Array Multiplication Works

  1. AND Array: Generate partial products: pp[i][j] = A[j] & B[i]
  2. Row 0: First partial product row = A & B[0]
  3. Row 1: (A & B[1]) << 1, added via full adders
  4. Row i: (A & B[i]) << i, accumulated through carry chain
  5. Final row: Remaining sum + carry → product bits
An N×N array multiplier uses N² AND gates, N(N-1) full adders, and N-1 half adders.

Resource Count

Verilog — Array Multiplier


                

            

        


        
        
        
        
        

            
🛠️ Logic Designer Build — Half Adder → Full Adder → N-bit Multiplier

            

                Each design is constructed in a NetlistModel using the subblock engine (LDL), then compiled and verified by simulation against an independent reference. The engine handles 2ⁿ cases automatically.
            


            

                
                
                
            


            
            

                
Half Adder: sum = a ⊕ b,   carry = a · b

                
                

                    

                        
Schematic (built from primitive gates)

                        

                    

                    

                        
Truth Table — 4 cases

                        

                        
Click "Build & Verify" to construct and simulate the half adder.